The subject matter of the present invention relates generally to circuitry for converting ECL logic level signals to corresponding CMOS logic level signals to permit the coupling of ECL circuits to CMOS circuits and to interface with logic circuit buffer drivers of the type that are used in networks where matched impedance terminated transmission line communications is required.
In order to couple an ECL circuit to a CMOS circuit, the difference between the output voltages from the first circuit and the input voltages needed by the second circuit, must be generated by some form of converter circuit.
In ECL circuits, the logic level "1" will approach -0.8 volts while the logic level "0" will approach -1.68 volts. For CMOS circuits, the logic level "1" will approach the power supply value, which is generally 3 to 5 volts, while the logic level "0" will be near the reference or ground level voltage.
Circuitry for performing such a conversion should contain as few transistors as possible in order to minimize the use of silicon area and also to minimize propagation delays through the transistors.
A patent of interest for its teaching in this art is U.S. Pat. No. 4,453,095, entitled "ECL MOS Buffer Circuits" by R. S. Wrathall. The circuit described in this patent is an input buffer for receiving on its input ECL logic signals and for providing at its output, CMOS signals.
Another patent of interest is U.S. Pat. No. 4,538,076, entitled "Level Converter Circuit" by H. Shinada. The circuit of this patent is a level converter for converting a first logic signal, using a lower voltage supply as a base potential, into a second logic signal having a higher voltage supply as a base potential.
Another patent of interest is U.S. Pat. No. 4,568,601, entitled "Level Conversion Input Circuit" by N. A. Kokubungi et al. The circuit of this patent converts an ECL logic level signal to a CMOS logic level signal. The circuit is adapted to provide a level conversion input which has high speed performance and low power consumption while being relatively stable as to the fluctuation of temperature and power source voltages.
Another patent of interest is U.S. Patent No. 4,437,171, entitled "ECL Compatible CMOS Memory" by E. L. Hudson et al. In this patent input buffers are provided with a comparator that is referenced to a biasing potential. The biasing potential is developed on the CMOS chipwwith bi-polar transistors, integrally formed during the CMOS processing. The comparator outputs the difference in the level of the ECL input signal as compared against the biasing network voltage, and by level shifting the difference between the signals provides the appropriate CMOS logic level signal.